module mcu_ahb_bus(
    		//复位，时钟
		input	wire		sclk,
		input	wire		resetb,
		input	wire		clk_mcu,

		//mcu ahb
		input	wire	[1:0]	HTRANS_EXT,
		input	wire	[31:0]	HADDR_EXT,
		input	wire		HWRITE_EXT,
		input	wire		HSEL_EXT,
		input	wire	[31:0]	HWDATA_EXT,
		input	wire	[2:0]	HSIZE_EXT,
		input	wire		HREADY_IN_EXT,
		output	wire	[1:0]	HRESP_EXT,
		output	wire		HREADY_OUT_EXT,
		output	wire	[31:0]	HRDATA_EXT,

		//给显示逻辑的参数设置
		output	reg		set_d_ok,
		output	wire	[31:0]	set_addr,
		output	wire	[7:0]	set_data,
		output	reg		set_r_req,
		input	wire	[7:0]	set_rdata,

		output	wire	[31:0]	tout
		);

//**********************************************/
//        	信号定义
/***********************************************/
reg		op_start, write_flag, op_ready;
reg	[3:0]	op_count;
reg		dout_load, din_load;

//**********************************************/
//        	总线处理
/***********************************************/
//AHB操作起始
always @(posedge sclk or negedge resetb)
	if (resetb == 0)
		op_start <= 0;
	else if ((HTRANS_EXT[1] == 1) && (clk_mcu == 0))
		op_start <= 1;
	else
		op_start <= 0;
		
//AHB操作延时计数
always @(posedge sclk or negedge resetb)
	if (resetb == 0)
		op_count <= 4'hF;
	else if (op_start == 1)
		op_count <= 0;
	else if (op_count[3] == 0)
		op_count <= op_count + 1;

//AHB操作类型保存
always @(posedge sclk or negedge resetb)
	if (resetb == 0)
		write_flag <= 0;
	else if ((HTRANS_EXT[1] == 1) && (clk_mcu == 0))
		write_flag <= HWRITE_EXT;

//AHB操作延时计数
always @(posedge sclk or negedge resetb)
	if (resetb == 0)
		op_ready <= 1'b1;
	else if (op_start == 1)
		op_ready <= 1'b0;
	else if (op_count >= 7 )
		op_ready <= 1'b1;
	else if ((write_flag == 1) && (op_count >= 3))
		op_ready <= 1'b1;

assign	HREADY_OUT_EXT = op_ready;
assign	HRESP_EXT = 2'b00;		//总线状态始终为ok
		
//AHB操作地址保存
always @(posedge sclk or negedge resetb)
	if (resetb == 0)
		set_addr <= 0;
	else if ((HTRANS_EXT[1] == 1) && (clk_mcu == 0))
		set_addr <= HADDR_EXT;
		
//设置总线写标志
always @(posedge sclk or negedge resetb)
	if (resetb == 0)
		set_d_ok <= 0;
	else if ((write_flag == 1) && (op_count == 4))
		set_d_ok <= 1;
	else
		set_d_ok <= 0;
		
//输出数据加载
always @(posedge sclk or negedge resetb)
	if (resetb == 0)
		dout_load <= 0;
	else
		dout_load <= op_start;
		
//输出数据加载
always @(posedge sclk or negedge resetb)
	if (resetb == 0)
		set_data <= 0;
	else if (dout_load == 1)
		set_data <= HWDATA_EXT;
		
//输入数据请求
always @(posedge sclk or negedge resetb)
	if (resetb == 0)
		set_r_req <= 0;
	else if (op_count == 0)
		set_r_req <= 1;
	else
		set_r_req <= 0;
		
//输入数据加载
always @(posedge sclk or negedge resetb)
	if (resetb == 0)
		din_load <= 0;
	else if (op_count == 6)
		din_load <= 1;
	else
		din_load <= 0;
		
//输入数据加载
always @(posedge sclk or negedge resetb)
	if (resetb == 0)
		HRDATA_EXT <= 0;
	else if (din_load == 1)
		HRDATA_EXT <= set_rdata;
		
//调试输出
assign	tout = 0;

endmodule
